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wide supply range, rail - to - rail output instrumentation amplifier preliminary technical data AD8226 rev. pra i n f o r m a t i o n f u r n i s h e d b y a n a l o g d e v i c e s i s b e l i e v e d t o b e a c c u r a t e a n d r e l i a b l e . h o w e v e r , n o r e s p o n s i b i l i t y i s a s s u m e d b y a n a l o g d e v i c e s f o r i t s u s e , n o r f o r a n y i n f r i n g e m e n t s o f p a t e n t s o r o t h e r r i g h t s o f t h i r d p a r t i e s t h a t m a y r e s u l t f r o m i t s u s e . s p e c i f i c a t i o n s s u b j e c t t o c h a n g e w i t h o u t n o t i c e . n o l i c e n s e i s g r a n t e d b y i m p l i c a t i o n o r o t h e r w i s e u n d e r a n y p a t e n t o r p a t e n t r i g h t s o f a n a l o g d e v i c e s . t r a d e m a r k s a n d r e g i s t e r e d t r a d e m a r k s a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s . one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 analog devices, inc. all rights reserved. features gain set with 1 external resistor gain r a n g e : 1 to 1 000 input voltage goes to ground input overdrive protection v e r y w ide power supply range dual s upply: 1.3 v t o 1 8 v single s upply: 2.6 v to 36 v b andw i d t h ( g = 1) : 800 khz cmrr (g = 1) : 7 8 db min imum i nput noise : 22 nv/r t(hz) t ypical s u p p l y c u r r e n t : 3 5 0 a soic - 8 and msop - 8 packages applications industrial process controls bridge amplifiers medical instrumentation portable data acquisition multi channel systems pin configuration top view (not to scale) 07036-001 Cin 1 r g 2 r g 3 +in 4 +v s 8 v o ut 7 ref 6 Cv s 5 AD8226 figure 1 . general description t h e a d 8 2 2 6 i s a l o w c o s t i n s t r u m e n t a t i o n a m p l i f i e r t h a t r e q u i r e s only one external resistor to set any gain between 1 and 1000. the AD8226 is designed to work with a very wide range of v o l t a g e s . it can operat e on supplies ranging from 1.2 v to 18 v (2.4 v to 36 v s i n g l e s u p p l y ) . the AD8226 comes with rail - to - ra il output and a wide input range that includes the ability to go slightly below the negative supply. in addition, the AD8226 input s can withstand vol tages beyond the rail. the AD8226 is perfect for multichannel, space - c o n s t r a i n e d a p p l i c a t i o n s . being a low power and low cost amplifier allows multiple channels to be used. the AD8226 has three grades. the a grade is the lower cost version and is spec ifi e d f o r t emperature s f r o m ? 40c to +85c . the b grade is the higher performance version and is specified from ?40c to +85c. the c grade version is the higher temperature version and is specified from ? 40 c to +105c. all models are operational from ? 40 c to + 125c ; behavio r a t these temperatures is shown in the typical performance curves . the AD8226 is available in msop and soic packages. table 1 . instrumentation amplifiers by category general purpose z e r o drift military grade l o w p o w e r hi gh s pee d pga ad8220 1 ad8231 1 ad620 ad627 1 ad8250 ad8221 ad8290 ad621 ad623 1 ad8251 ad8222 ad8293 1 ad524 AD8226 1 ad8253 ad8224 1 ad8553 1 ad526 ad8228 ad855 6 1 ad624 ad8557 1 1 r a i l - to - rail output.
AD8226 preliminary technical data rev. pra | p a g e 2 of 16 table of contents features ................................ ................................ .............................. 1 a p p l i c a t i o n s ................................ ................................ ....................... 1 pin configuration ................................ ................................ ............. 1 general description ................................ ................................ ......... 1 specifications ................................ ................................ ..................... 3 absolute maximum ratings ................................ ............................ 7 thermal resistance ................................ ................................ ...... 7 e s d c a u t i o n ................................ ................................ .................. 7 pin configuration and function descriptio n s ............................. 8 t h e o r y o f o p e r a t i o n ................................ ................................ ........ 9 a r c h i t e c t u r e ................................ ................................ ................... 9 gain selection ................................ ................................ ................ 9 i n p u t p r o t e c t i o n ................................ ................................ ............ 9 r eference terminal ................................ ................................ .... 10 input vol t a ge r a nge ................................ ................................ ... 10 l a y o u t ................................ ................................ .......................... 10 input bias current return path ................................ ............... 11 radio frequency interfe rence (rfi) ................................ ........ 11 o u t l i n e d i m e n s i o n s ................................ ................................ ....... 12 ordering guide ................................ ................................ .......... 13
preliminary technical data AD8226 rev. pra | p a g e 3 of 16 specifications +v s = + 15 v, ? v s = ? 15 v, v ref = 0 v, t a = 25 c , g = 1, r l = 10 k, unless otherwise noted . table 2 . parameter conditions a, c grade b grade unit min typ max min typ max common - m o d e rejection ratio (cmrr) cmrr dc to 60 hz v cm = C 10 v to +10 v g = 1 7 6 86 db g = 10 90 100 db g = 100 105 105 db g = 1000 105 105 db noise total n ois e : e n = e ni 2 + ( e no / g 2 ) voltage noise, 1 khz input voltage noise, e ni v in+ , v in ? , v ref = 0 22 22 nv/ hz output voltage noise, e n o 120 120 nv/ hz rti f = 0.1 hz to 10 hz g = 1 3 3 v p - p g = 10 0.8 0.8 v p - p g = 100 to 1000 0.6 0.6 v p - p c u r re n t n o i s e f = 1 khz 100 100 fa/ hz f = 0.1 hz to 10 hz 3 3 pa p - p voltage offset total offset v oltage : v os = v o s i + (v o s o /g ) input offset, v osi v s = 5 v to 15 v 500 200 v over temperature t a = t min t o t max v average temperature coefficient t a = t min t o t max output offset, v o s o v s = 5 v to 15 v 1500 750 v over temperature t a = t min t o t max mv average temperature coefficient t a = t min t o t max 2 15 2 7 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 80 90 db g = 10 100 105 db g = 100 105 105 db g = 1000 105 105 db input current input bias current 10 20 30 10 20 30 na over temperature t a = t min t o t max 5 40 5 40 na average temperature coefficient t a = t min t o t max 100 100 pa/c input offset current 3 2 na over temperature t a = t min t o t ma x 5 5 na average temperature coefficient t a = t min t o t max 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ? v s +v s ? v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 %
AD8226 preliminary technical data rev. pra | p a g e 4 of 16 parameter conditions a, c grade b grade unit min typ max min typ max dynamic response small signal C 3 db bandwidth g = 1 1000 1000 khz g = 10 150 150 khz g = 1 00 15 15 khz g =1000 1.5 1.5 khz settling time 0.01% 10 v step g = 1 22 22 s g = 1 0 22 22 s g = 100 50 50 s g = 1000 600 600 s slew rate g = 1 0.5 0.5 v/s g = 5 to 100 1 1 v/s gain g = 1 + (49.4k /r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.07 0.02 % g = 10 0.3 0.1 % g = 100 0.3 0.1 % g = 1000 0.3 0.1 % gain nonlinearity v out = C 10 v to +10 v g = 1 r l = 10 k ppm g = 100 r l = 10 k ppm g = 1000 r l = 10 k ppm g = 1 - 100 r l = 2k ppm gain vs. temperature g = 1 t a = t min t o t max 2 10 2 5 ppm/c g > 1 1 t a = t min t o t max C 50 C 50 ppm/c input v s = 1. 35 v to 36 v input impedance differential 2||2 2||2 g ||pf common mode 2||2 2||2 g ||pf input operating voltage range 2 t a = 25c ? v s ? 0.1 +v s ? 0.7 ? v s ? 0.1 +v s ? 0.7 v t a = C 40c ? v s ? 0.15 +v s ? 0. 9 ? v s ? 0.15 +v s ? 0. 9 v t a = 105c ? v s ? 0.05 +v s ? 0. 6 ? v s ? 0.05 +v s ? 0. 6 v input overvoltage range t a = t min t o t max +v s ? 40 ? v s +40 +v s ? 40 ? v s +40 v output v s = 1.35 v to 36 v output swing r l = 10 k to ground ? v s + 0. 2 +v s ? 0.2 ? v s + 0.2 ? v s + 0. 2 v over temperature t a = t min t o t ma x ? v s + 0.3 +v s ? 0.3 ? v s + 0.3 +v s ? 0.3 v output swing r l = 100 k to ground ? v s + 0. 1 + v s ? 0. 1 ? v s + 0. 1 ? v s + 0. 1 v over temperature t a = t min t o t max ? v s + 0.1 +v s ? 0.1 ? v s + 0.1 ? v s + 0.1 v short - circuit current 13 13 ma power supply operating range dual supply operation 1.3 18 1.3 18 v quiescent current 350 400 350 400 a over temperature t a = t min t o t max a temperature range specified performance: t m i n to t m a x a and b grades C 40 +85 ? 40 +85 c c grade C 40 +105 operational C 40 +125 ? 40 +125 c 1 does not include the effects of external resistor r g 2 input voltage range of th e AD8226 input stage. input range depends on common mode voltage, differential voltage, gain, and reference voltage. s e e t h e input v o l t a g e r a n g e section in the theory of operation for more information.
preliminary technical data AD8226 rev. pra | p a g e 5 of 16 +v s = 2.7 v , C v s = 0 v , v ref = 0 v , t a = 25c, g = 1, r l = 10 k , unless otherwise noted. table 3 . parameter conditions a,c grade b grade unit min typ max min typ max common - m o d e rejection ratio (cmrr) cmrr dc to 60 hz v cm = 0 v to 1.7 v g = 1 7 6 86 db g = 10 90 100 db g = 100 105 105 db g = 1000 105 105 db noise total nois e : e n = e ni 2 + ( e no / g 2 ) voltage noise, 1 khz input voltage noise, e ni v in+ , v in ? , v ref = 0 22 22 nv/ hz output voltage noise, e n o 120 120 nv/ hz rti f = 0.1 hz to 10 hz g = 1 3 3 v p - p g = 10 0.8 0.8 v p - p g = 100 to 1000 0.6 0.6 v p - p c u r re n t n o i se f = 1 khz 100 100 fa/ hz f = 0.1 hz to 10 hz 3 3 pa p - p voltage offset total offset voltage : v os = v o s i + (v o s o /g ) input offset, v osi v s = 0 v to 1.7 v 300 150 v over temperature t a = t min t o t max v average tc t a = t min t o t max 0.1 4 0.1 2 v/c output offset, v o s o v s = 0 v to 1.7 v 1200 750 v over temperature t a = t min t o t max mv average tc t a = t min t o t max 2 15 2 7 v/c offset rti vs. supply (psr) v s = 0 v to 1.7 v g = 1 80 90 db g = 10 100 105 db g = 100 105 105 db g = 1000 105 105 db input current input bias current 10 20 30 10 20 30 na over temperature t a = t min t o t max 5 40 5 40 na average tc t a = t min t o t max 100 100 pa/c input offset current 3 2 na over temperature t a = t min t o t max 5 5 na average tc t a = t min t o t max 5 5 pa/c reference input r in 100 100 k i in 7 7 a voltage range ? v s +v s ? v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 % dynamic response small signal C 3 db bandwidth g = 1 1000 1000 khz g = 10 150 150 khz g = 100 15 15 khz g =1000 1.5 1.5 khz
AD8226 preliminary technical data rev. pra | p a g e 6 of 16 parameter conditions a,c grade b grade unit min typ max min typ max settling time 0.01% 2 v step g = 1 22 22 s g = 1 0 22 22 s g = 100 50 50 s g = 1000 600 600 s slew rate g = 1 0.5 0.5 v/s g = 5 to 100 1 1 v/s gain g = 1 + (49.4 k /r g ) gain range 1 1000 1 1000 v/v gain error v out = 0 v to 1.7 v g = 1 0.07 0.02 % g = 10 0.3 0.1 % g = 100 0.3 0.1 % g = 1000 0.3 0.1 % gain nonlinearity v out = 0 v to 1.7 v g = 1 r l = 10 k ppm g = 100 r l = 10 k ppm g = 1000 r l = 10 k ppm g = 1 - 100 r l = 2 k ppm gain vs. temperature g = 1 t a = t min t o t max 2 10 2 5 ppm/c g > 1 1 t a = t min t o t max ? 50 C 50 ppm/c input ? v s = 0v; +v s = 2.7 v to 36 v input impedance differential 2||2 2||2 g ||pf common mode 2||2 2||2 g ||pf input operating voltage range 2 t a = 25c ? 0.1 +v s ? 0.7 ? 0.1 +v s ? 0.7 v t a = C 40c ? 0.15 +v s ? 0.9 ? 0.15 +v s ? 0.9 v t a = 105c ? 0.05 +v s ? 0.6 ? 0.05 +v s ? 0.6 v input overvoltage range t a = t min t o t max +v s ? 40 ? v s +40 +v s ? 40 ? v s +40 output ? v s = 0v; +v s = 2.7 v to 36 v output swing r l = 10 k to opposite supply 0.2 +v s ? 0.2 0.2 ? v s + 0.2 v over temperature t a = t min t o t max 0.3 +v s ? 0.3 0.3 +v s ? 0.3 v output swing r l = 100 k to opposite supply 0.1 +v s ? 0.1 0.1 ? v s + 0.1 v over temperature t a = t min t o t max 0.1 +v s ? 0.1 0.1 ? v s + 0.1 v short - circuit current 13 13 ma power supply operating range s ingle supply operation 2.6 36 2.6 36 v quiescent current 300 350 300 350 a over temperature t a = t min t o t max a temperature range specified performance: t m i n to t m a x a and b grades C 40 +85 C 40 +85 c c grade C 40 +105 ope rational C 40 +125 C 40 +125 c 1 does not include the effects of external resistor r g 2 input v oltage range of the AD8226 input stage. input range depends on common mode voltage, differential voltage, gain, and reference volt age. s e e t h e input v o l t a g e r a n g e section in the theory of operation for more information.
preliminary technical data AD8226 rev. pra | p a g e 7 of 16 absolute maximum rat ings table 4 . parameter rating supply voltage 18 v output short - circuit current indefinite maximum voltage at ? in or +in ? vs + 40v minimum voltage at ? in or +in +vs ? 40v r e f v o l t a g e v s differential input voltage 40v storage temperature range ?65c to +150c operating temperature range 1 ?40c to +125c maximum junction temperature 1 40c esd human body m odel 2 kv charge device model 1 kv 1 temperature range for specified performance is either ?40c to + 8 5 c or ? 4 0 c t o + 10 5c , depending on grade. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational se ction of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance j a is specified for a device in free air. table 5 . package ja unit 8 - lead msop, 4 - layer jedec board 135 c/w 8 - l e a d s o i c , 4 - layer jedec board 121 c/w esd caution
AD8226 preliminary technical data rev. pra | p a g e 8 of 16 pin configuration an d function descripti ons top view (not to scale) 07036-002 Cin 1 r g 2 r g 3 +in 4 +v s 8 v o ut 7 ref 6 Cv s 5 AD8226 figur e 2 . pin configuration table 6 . pin function descriptions p i n n o . mnemonic description 1 ?in negative input. 2, 3 r g gain setting pins . pl ace g ain res is t or b et we e n t h es e t wo p i n s. 4 +in positive input. 5 ?v s negative supply. 6 ref reference. must be driven by low impedance. 7 v out output. 8 +v s positive supply.
preliminary technical data AD8226 rev. pra | p a g e 9 of 16 theory of operation a3 r2 2.47k? r1 2.47k? a1 a2 +v s Cv s q2 q1 Cin +in +v s Cv s +v s Cv s r3 50k? r4 50k? r5 50k? r b r b +v s Cv s out ref 07036-003 node 1 node 2 r g u b +v s Cv s +v s Cv s node 4 node 3 r6 50k? difference amplifier s t age gain s t age figure 3 . simplified schemati c architecture the ad82 26 is based on the classic three op a m p t o p o l o g y. t h i s topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier to remove the common - mode voltage. f i g u r e 3 s h ow s a s i m pl i f i e d schematic of the ad82 26 . the f irst stage works as follows : i n o r d e r to maintain a constant voltage across the bias resistor r b , am plifier a1 must keep node 3 a constant diode drop above the positive input voltage. similarly, amplifier a2 keeps node 4 at a constant diode drop above the negative input voltage. therefore a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows across this resistance must also flow through the r1 and r2 resistors, creating a gained differential signa l between the a2 and a1 outputs. note that, in addition to a gained differential signal, the original common - mode signal, shifted a diode drop down, is also still present. the second stage is a difference amplifier, composed of a 3 and four 50 k? resistors. the purpose of this stage is to remove the c o m m o n - mode signal from the amplified differential signal. because the input amplifiers employ a current feedback architecture, the gain - bandwidth product of the AD8226 increases with g ain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains. the transfer function of the ad822 6 is v out = g ( v in+ ? v in? ) + v ref where g r g k 49.4 1 + = gain selection p l a c i n g a resistor across the r g terminals sets the gain o f t h e AD8226 , which can be calculated by referring to t a b l e 7 o r b y using the following gain eq u a t i o n : 1 k 49.4 ? = g r g table 7 . gains achieved sing 1 resistors 1% standard table value of r g (?) calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the AD8226 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be a dded to the AD8226s specifications to determine the total gain accuracy of the system. w hen the gain resistor is not used , g ain error and gain drift are minimal . input protection the input terminals of the AD8226 have input protection that allows the i n p ut voltage to go beyond the rails without damaging the part . maximum voltage is C vs+40 v and minimum voltage is +vs - 40 v . for example: with 15 v supplies, the part can withstand input voltages of 25 v; with a 5 v single supply, maximum input voltage is 40 v a nd minimum input voltage is 35 v .
AD8226 preliminary technical data rev. pra | p a g e 10 of 16 reference terminal the output voltage of the AD8226 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for e x a m p l e, a voltage source can be tied to the ref pin to level - shi ft the output so that the AD8226 can drive a single - supply adc. the ref pin is protected with esd diodes and should not exceed either +v s o r ? v s by more than 0.3 v . f o r the best performance, source impedance to the ref terminal should be kept be l o w 2 ? . as shown in f i g u r e 3 , the reference ter minal, ref, is at one end of a 5 0 k resistor. additional impedance at the ref terminal adds to this 5 0 k resistor and results in amplification of the signal connected to the positive input. the amplification from the addition al r ref can be computed by 2(50 k + r ref )/100 k + r ref . only the positive signal p ath is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct AD8226 op1177 + C v 07036-004 ref AD8226 ref figure 4 . driving the reference pin input voltage range the three o p amp architecture of the AD8226 applies gain in the first stage bef ore removing c o m m o n - m o d e v o l t a g e in the difference amplifier s t a ge . in addition, the input transistors in the first stage shift the common mode voltage up one diode drop (about 650 mv.) therefo re, internal nodes between the first and second stages (n odes 1 and 2 in f i g u r e 3 ) experience a c o m b i n a t i o n o f gained signal , c o m m o n - mode signal , and 650 mv . this combined signal can be limited by the voltage supplies even when the individual input and output signals are n o t . f i g u r e x x through f i g u r e x x show the allowable c o m m o n - mode input voltage rang e s f o r v a r i o u s o u t p u t v o l t a g e s an d s upply v olt a ge s . the following formulas can also be used to understand how the reference voltage (v ref ), common mode input voltage (v cm ), and differential input voltage (v diff ) interact. the se t w o formulas, along with the input range specifications in t a b l e 1 and t a b l e 3 , s et the boundaries where the part o perates with best p erformance. v 9 . 0 2 ) )( ( v 4 . 0 ? + < + < ? ? s cm diff s v v gain v v v v v v gain v s ref cm diff .6 1 2 2 ) )( ( ? + < + + t h e c o m m o n - mode input range shifts upwa rds with temper - a t u r e . at cold temperatures, the part requires an extra 200 mv o f h e a d r o o m f r o m t h e positive supply, and operation near the ne gative supply has more margin. c o n v e r s e l y, h o t temperatures r e q u i r e l e s s h e a d r o o m f r o m t h e p o s itive supply, but are the wor st - case conditions for input voltages near the negative supply. layout to ensure optimum p erformance of the AD8226 at the pcb level, care must be taken in the design of the board layout. the ad822 6 pins are arranged in a logical manner to aid in this task. 8 7 6 5 1 2 3 4 Cin r g r g +v s v o ut ref Cv s +in t o p view (not to scale) AD8226 07036-005 figure 5 . pinout diagram common - mode rejection ratio over frequency po or layout can cause some of the common - mo de si gn al s t o b e converted to differential signal s before r e a c h i n g the in - a m p . such conversions occur when one input path has a frequency response t h a t i s d i f f e r e n t f r o m t h e o t h e r . to k e e p c m r r a c r o s s f r e q u e n c y h i g h , i nput source impedance and capacitance of each path should be closely matched. additional source resistance in t h e i n p u t p a t h ( f o r e x a m p l e , f o r i n p u t p r o t e c t i o n ) s h o u l d b e p l a c e d close to the in - amp inputs, which minimizes their interaction w ith parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency . if the board design has a component at the gain setting pins (for example, a switch or jumper), the part should be chosen so that the parasitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the instrumenta - t i o n amplifie r. noise on the supply pins can adversely af fect p e r f o r m ance. a 0.1 f capacitor should be placed as close as possible to each s u p p l y p i n . as shown in f i g u r e 6 , a 10 f tantalum capacitor can be used fa r ther away from the part. in most cases, i t can be shared by other precision integrated circuits.
preliminary technical data AD8226 rev. pra | p a g e 11 of 16 AD8226 +v s +in Cin load ref 0.1 f 10 f 0.1 f 10 f Cv s v o ut 07036-006 figure 6 . supply decoupling, ref, and output referred to local ground reference s the output voltage of the ad822 6 is developed with respect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground. input bias current r eturn path the input bias current of the ad822 6 must have a return path to g r o u n d . when the source, such as a thermoc o u p l e , c a n n o t provide a return current path, one should be created, as shown in f i g u r e 7 . thermocouple +v s ref Cv s AD8226 capacitively coupled +v s ref c c Cv s AD8226 transformer +v s ref Cv s AD8226 incorrect capacitively coupled +v s ref c r r c Cv s AD8226 1 f hi g h- pass = 2rc thermocouple +v s ref Cv s 10m? AD8226 transformer +v s ref Cv s AD8226 correct 07036-007 figure 7 . creating an i b i a s path r a d i o f r e q u e n c y interference (rfi) rf rectification is often a problem when a mplifiers are used in a p p l i c a t i o n s h a v i n g s t r o n g r f s i g n a l s . t h e d i s t u r b a n c e c a n a p p e a r a s a s m a l l d c o f f s e t v o l t a g e . h i g h f r e q u e n c y s i g n a l s c a n b e f i l t e r e d with a low - pass rc network placed at the input of the instru - mentation amplifier, as shown in f i g u r e 8 . the f i l t e r l i m i t s t h e i n p u t s i g n a l b a n d w i d t h , a c c o r d i n g t o t h e f o l l o w i n g r e l a t i o n s h i p : filter frequency diff = ) 2 ( 2 1 c d c c r + filterfrequency cm = c rc 2 1 where c d 10 c c . r r AD8226 +v s +in Cin 0.1f 10f 10f 0.1f ref v o ut Cv s r g c d 10nf c c 1nf c c 1nf 4.02k? 4.02k? 07036-008 figure 8 . rfi suppression c d a f f e c t s t h e d i f f e r e n c e s i g n a l , a n d c c a f f e c t s t h e c o m m o n - m o d e signal. values of r and c c should be chosen to minimize rfi. m i s m a t c h b e t w e e n t h e r c c a t t h e p o s i t i v e i n p u t a n d t h e r c c a t t h e n e g a t i v e i n p u t d e g r a d e s t h e c m r r o f t h e a d 8 2 2 6 . b y u s i n g a value of c d one magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved.
AD8226 preliminary technical data rev. pra | p a g e 12 of 16 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 9 . 8 - lead mi ni small outline package [msop] (rm - 8) dimensions sh own in millimeters controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-a a 012407- a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) se a ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarit y 0.10 figure 10 . 8 - lead standard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches)
preliminary technical data AD8226 rev. pra | p a g e 13 of 16 ordering guide model temperature range package description package opt i on branding ad8 226 armz 1 C 40c to +85c 8 - lead msop rm - 8 y16 AD8226 armz - rl 1 C 40c to +85c 8 - lead msop, 13" tape and reel rm - 8 y16 AD8226 armz - r7 1 C 40c to +85c 8 - lead msop, 7" tape and reel rm - 8 y16 AD8226 arz 1 C 40c to +85c 8 - l e a d soic_n r - 8 AD8226 arz - rl 1 C 40c to +85c 8 - l e a d soic_n , 13" tape and reel r - 8 AD8226 arz - r7 1 C 40c to +85c 8 - l e a d soic_n , 7" tape and reel r - 8 AD8226 brmz 1 C 40c to +85c 8 - lead msop rm - 8 y1m AD8226 brmz - rl 1 C 40c to +85c 8 - lead msop, 13" tape and reel rm - 8 y1m AD8226 brmz - r7 1 C 4 0c to +85c 8 - lead msop, 7" tape and reel rm - 8 y1m AD8226 brz 1 C 40c to +85c 8 - l e a d soic_n r - 8 AD8226 brz - rl 1 C 40c to +85c 8 - l e a d soic_n , 13" tape and reel r - 8 AD8226 arz - r7 1 C 40c to +85c 8 - l e a d soic_n , 7" tape and reel r - 8 AD8226 crmz 1 C 40c to +10 5c 8 - lead msop rm - 8 y1y AD8226 crmz - rl 1 C 40c to +10 5c 8 - lead msop, 13" tape and reel rm - 8 y1y AD8226 crmz - r7 1 C 40c to +10 5c 8 - lead msop, 7" tape and reel rm - 8 y1y AD8226 crz 1 C 40c to +10 5c 8 - l e a d soic_n r - 8 AD8226 crz - rl 1 C 40c to +10 5c 8 - l e a d soic_n , 13" tape and reel r - 8 AD8226 crz - r7 1 C 40c to +10 5c 8 - l e a d soic_n , 7" tape and reel r - 8 1 z = rohs compliant part.
AD8226 preliminary technical data rev. pra | p a g e 14 of 16 notes
preliminary technical data AD8226 rev. pra | p a g e 15 of 16 notes
AD8226 preliminary technical data rev. pra | page 16 of 16 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr07036-0-10/08(pra)

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